Advanced integrated circuits (ICs) consist of several circuits requiring different clock frequencies. The clock frequency is generated dynamically, based on a divider value generated using a system software. The divider value is placed on a bus which is asynchronous to a control clock input of the IC. Whenever a different clock frequency is desired, the system software changes the divider value placed on the asynchronous bus to change the clock frequency.
Synchronizing the asynchronous bus to the control clock input of the IC is challenging, as the control clock input is generated by a hardware that controls the IC. Since the hardware controls given to the control clock input are different from the system software controls, the system software could change the divider value when the control clock input is gated. The problem of synchronization is further complicated with the requirement that notwithstanding the gated control clock input, the latest change in the divider value must take effect. Further, when there is more than one change to the divider value in quick succession, it is necessary that the latest change is addressed irrespective of the intermediate changes.